Z-Wave Hardware Best Practices

This is an abbreviated version of the full blog on the Z-Wave Alliance website.

Introduction

Cost sensitive wireless smart home devices have different requirements compared to designing cell phones or laptops. The printed circuit boards (PCB) are usually only a few square inches and often only two layers. To fit inside of an electrical outlet box the entire product must be small and cost considerations require integrated microcontrollers to supply most of marketings requirements.

Basics of IoT Device Hardware

A key feature of having the engineer do the PCB design, is that the engineer can easily change the MCU pinout to solve PCB layout problems. Since both Silicon Labs and Trident IoTs Z-Wave chips can route nearly any peripheral to almost any GPIO, I often swap GPIOs while routing the PCB. Make a quick change to the schematic, reread the netlist in the layout tool and voilà, problem solved! Just remember to also change the pinout in the firmware.

I usually manually design, layout and hand-assemble prototypes. If I need to build more than five, I contract assembly out because assembly quickly becomes a huge time sink. I use the open source KiCAD electronic design software. I have contributed a few library components to the repo including the Silicon Labs ZG23 and Tridents CZ20. Many PCB vendors can directly import KiCAD files, but I prefer to send them good ol’ Gerber files to ensure I get exactly what I want. With the KiCAD files, the vendor may adjust parameters such as the solder mask clearance which results in no solder mask between the fine pitch pins of the MCU resulting in nothing but solder shorts between the tiny pins. I don’t even use the autorouter as it tends to make a mess of things with way too many vias. The routing is usually simple enough to complete in a few hours and is an enjoyable game of close-the-rats-nets.

Keeping Costs Low

The main cost driver for consumer electronics is volume. The higher the annual volume, the lower the cost for nearly every line item; PCB manufacturing, the MCU, passives, ICs, assembly, test and packaging. If the product volume isn’t at least in the 10K units/year range, then it must be unique enough to command a high price. There is a significant knee-of-the-curve at the 10k threshold.

Don’t spend too much time checking, rechecking, and reviewing the schematic and layout. The turnaround time for a new prototype PCB can be as little as overnight, and the cost of a new board is just a few dollars. Thus, it makes sense to send the board out quickly and expect to spin it once or twice to fix a couple of errors. I accidentally put the wrong size passive component on the board and only discovered the mistake when it barely fits in the footprint on the board. But that’s easily fixed and a new board is ready next week. I’ve also reversed the pinout of a connector or some other special component that gives the bottom view in the datasheet instead of the top view. Again, easily fixed and I have new boards in about a week. Be careful with GPIO selection as the 800 series has limitations on power domain and wakeup capabilities of certain pins. See my GPIO blog for more details.

Rules for low-cost IoT products

Naturally these “rules” are not absolute requirements but instead are recommendations. Engineering is the art of balancing the solution to meet the requirements in a cost-efficient manner. Often it is worthwhile to push back on a requirement if the cost is too high so don’t simply accept the requirements as non-negotiable. The first rule here is an example of these engineering tradeoffs: a four-layer PCB is more expensive, but you get better impedance (thus better RF) and likely a smaller PCB. The balance between 2 vs. 4 layers is unique for every product which means it must be engineered.

1. Minimize PCB layers
   1. 2 works for most Z-Wave designs
   2. 4 costs ~40% more for bare PCB but has better impedance/RF
2. Minimize size
   1. PCB costs are computed by the square millimeter
   2. Remember the GND plane of the PCB is half of the antenna
3. Rectangular outline
   1. Simple shapes maximizes array utilization
   2. Ideally v-scored for minimal waste
4. 0.16-0.20mm (6-8mil) wire spacing
   1. Follow the design rules of the low-cost PCBs manufacturer
5. Minimize special holes
   1. Slots, unusual sizes, edge features all cost $
6. All SMT components on one side – cheaper, easier and higher yield
7. Use 0402/0603 passive components with enough space for easy Pick&Place
   1. 0201s are the size of a grain of sand – difficult to manage
   2. Larger sizes cost more with no significant benefit
8. Minimize manual assembly, wiring & soldering
9. PCB cost is driven by turnaround time
   1. Waiting for an extra week saves money

PCB Design Recommendations

• Use the Mini Simplicity debug footprint
  • Avoid custom footprints!
    • Requires fragile & expensive jig for debug/production
  • Use the standard Tag-Connect footprint & cable
    • The spring post cable has alignment pins enabling reliable programming and test
  • Ideally make the footprint visible under a battery door to allow (re)programming after the device has been inserted into the enclosure.
• No wires under the RF traces
  • Ideally all RF traces are all on component side
  • Minimize vias on RF traces which are impedance discontinuities
  • Surround RF traces with ground vias
• Use the vendor recommended crystals as they have been vetted by the vendor
• Continuous Ground fills
  • Ideally have a continuous ground fill on the back for better RF
• Add thru-hole vias to the VCOM TX signal
  • See when printfs are coming out on a scope compared to current consumption
  • Can be done by making a via larger (1mm)
• Connect extra GPIOs to thru-hole test points
  • Accessible from both sides of the PCB
  • Easily prototype hardware changes or future features
• Add a hardware version GPIO Resistor Divider Pair or capacitor
  • High ohms so little currentVersion 1=pulled up, Version 2=pulled down
  • Version 3 onward uses the ADC to measure voltage or a cap and a timer
• Review the ground plane flood fills
  • Ensure current paths do not require changing layers – No antennas – No floating areas
  • Array vias between top and bottom
• Avoid wires under the Z-Wave chip
  • The EP prevents this anyway
• Silkscreen signal names on connectors and test points
• All ground connections must have thermal reliefs
  • WSTK has several pins flood filled to a thru-hole connector – nearly impossible to solder!
• Analog has special rules! Follow them!
• Have a checklist, follow it, add new items to avoid previous mistakes
  • DRC rules must pass
  • All nets routed

See my public ZRAD github repo for detailed procedures for going from schematics to PCB layout to assembling prototypes.

Next Steps

Part 7 of the Z-Wave Developer’s Journey discusses how to debug and optimize battery life. Matching the proper type of battery to the needs of your product and achieving the desired battery life requires classic engineering skills. I’ll go over a few tips from my years of optimizing coin cell battery devices to last for years. As we continue along the Z-Wave Developer’s Journey, I welcome your comments and questions.  Please feel free to reach out to me directly via email.